LAYOUT DESIGNING METHOD

LAYOUT DESIGNING METHOD

PURPOSE:To reduce an entire layout area by eliminating generation of deterioration of signal due to a long wiring caused by automatic layout using a standard cell and noise such as coupling. CONSTITUTION:In the automatic layout using a standard cell, feed cells F1, f2, F3, F4, and F5 are used for el...

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1. Verfasser: MUTOU MASAHITO
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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description PURPOSE:To reduce an entire layout area by eliminating generation of deterioration of signal due to a long wiring caused by automatic layout using a standard cell and noise such as coupling. CONSTITUTION:In the automatic layout using a standard cell, feed cells F1, f2, F3, F4, and F5 are used for eliminating non-wiring. By configuring the feed cells F1, F2, F3, F4, and F5 with buffers, no long wiring over cell stages exists, which means that generation of feedthrough current due to signal deterioration and noise such as coupling can be eliminated. Also, by reducing the wiring load, a gate width W of a transistor constituting standard cells S1, S2, S3, S4, and S5 can be reduced, thus miniaturizing the entire chip.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title LAYOUT DESIGNING METHOD
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