VERIFYING METHOD FOR INTEGRATED CIRCUIT MASK PATTERN
PURPOSE:To provide the verifying method of an integrated circuit mask pattern capable of performing verification in a short processing time by performing an efficient arithmetic operation. CONSTITUTION:The circuit connection information of a first system extracted from the mask pattern and the circu...
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| creator | SHIMOHAKAMADA NAOKI JINBO YASUO |
| description | PURPOSE:To provide the verifying method of an integrated circuit mask pattern capable of performing verification in a short processing time by performing an efficient arithmetic operation. CONSTITUTION:The circuit connection information of a first system extracted from the mask pattern and the circuit connection information of a second system extracted from a circuit diagram are compared and collated in order to verify whether the circuit diagram and the mask pattern designed based on the circuit diagram are equivalent or not (S30). In order to obtain the circuit connection information of the first system, the mask pattern is digitized and inputted (512) and a cell not requiring the verification is specified (S15). Then, a circuit connection information extraction processing (S17) is performed only for the outside of the specified cell, a pseudo circuit is generated (S40) and the circuit connection information of the pseudo circuit is fitted and synthesized for the inside of the specified cell (S18). The information of the part of the specified cell is replaced with the circuit connection information of the pseudo circuit for the circuit connection information of the second system (S23.) By comparing the final circuit connection information of the first system and the second system, the verification for the part except the specified cell can be performed. |
| format | Patent |
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CONSTITUTION:The circuit connection information of a first system extracted from the mask pattern and the circuit connection information of a second system extracted from a circuit diagram are compared and collated in order to verify whether the circuit diagram and the mask pattern designed based on the circuit diagram are equivalent or not (S30). In order to obtain the circuit connection information of the first system, the mask pattern is digitized and inputted (512) and a cell not requiring the verification is specified (S15). Then, a circuit connection information extraction processing (S17) is performed only for the outside of the specified cell, a pseudo circuit is generated (S40) and the circuit connection information of the pseudo circuit is fitted and synthesized for the inside of the specified cell (S18). The information of the part of the specified cell is replaced with the circuit connection information of the pseudo circuit for the circuit connection information of the second system (S23.) By comparing the final circuit connection information of the first system and the second system, the verification for the part except the specified cell can be performed.</description><edition>5</edition><language>eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; BASIC ELECTRIC ELEMENTS ; CALCULATING ; CINEMATOGRAPHY ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; ELECTROGRAPHY ; HOLOGRAPHY ; MATERIALS THEREFOR ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940422&DB=EPODOC&CC=JP&NR=H06110974A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940422&DB=EPODOC&CC=JP&NR=H06110974A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHIMOHAKAMADA NAOKI</creatorcontrib><creatorcontrib>JINBO YASUO</creatorcontrib><title>VERIFYING METHOD FOR INTEGRATED CIRCUIT MASK PATTERN</title><description>PURPOSE:To provide the verifying method of an integrated circuit mask pattern capable of performing verification in a short processing time by performing an efficient arithmetic operation. CONSTITUTION:The circuit connection information of a first system extracted from the mask pattern and the circuit connection information of a second system extracted from a circuit diagram are compared and collated in order to verify whether the circuit diagram and the mask pattern designed based on the circuit diagram are equivalent or not (S30). In order to obtain the circuit connection information of the first system, the mask pattern is digitized and inputted (512) and a cell not requiring the verification is specified (S15). Then, a circuit connection information extraction processing (S17) is performed only for the outside of the specified cell, a pseudo circuit is generated (S40) and the circuit connection information of the pseudo circuit is fitted and synthesized for the inside of the specified cell (S18). The information of the part of the specified cell is replaced with the circuit connection information of the pseudo circuit for the circuit connection information of the second system (S23.) By comparing the final circuit connection information of the first system and the second system, the verification for the part except the specified cell can be performed.</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>CINEMATOGRAPHY</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>ELECTROGRAPHY</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1994</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAJcw3ydIv09HNX8HUN8fB3UXDzD1Lw9AtxdQ9yDHF1UXD2DHIO9QxR8HUM9lYIcAwJcQ3y42FgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BHgZmhoYGluYmjsbEqAEA2pYntA</recordid><startdate>19940422</startdate><enddate>19940422</enddate><creator>SHIMOHAKAMADA NAOKI</creator><creator>JINBO YASUO</creator><scope>EVB</scope></search><sort><creationdate>19940422</creationdate><title>VERIFYING METHOD FOR INTEGRATED CIRCUIT MASK PATTERN</title><author>SHIMOHAKAMADA NAOKI ; JINBO YASUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH06110974A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1994</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>CINEMATOGRAPHY</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>ELECTROGRAPHY</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SHIMOHAKAMADA NAOKI</creatorcontrib><creatorcontrib>JINBO YASUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHIMOHAKAMADA NAOKI</au><au>JINBO YASUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>VERIFYING METHOD FOR INTEGRATED CIRCUIT MASK PATTERN</title><date>1994-04-22</date><risdate>1994</risdate><abstract>PURPOSE:To provide the verifying method of an integrated circuit mask pattern capable of performing verification in a short processing time by performing an efficient arithmetic operation. CONSTITUTION:The circuit connection information of a first system extracted from the mask pattern and the circuit connection information of a second system extracted from a circuit diagram are compared and collated in order to verify whether the circuit diagram and the mask pattern designed based on the circuit diagram are equivalent or not (S30). In order to obtain the circuit connection information of the first system, the mask pattern is digitized and inputted (512) and a cell not requiring the verification is specified (S15). Then, a circuit connection information extraction processing (S17) is performed only for the outside of the specified cell, a pseudo circuit is generated (S40) and the circuit connection information of the pseudo circuit is fitted and synthesized for the inside of the specified cell (S18). The information of the part of the specified cell is replaced with the circuit connection information of the pseudo circuit for the circuit connection information of the second system (S23.) By comparing the final circuit connection information of the first system and the second system, the verification for the part except the specified cell can be performed.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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| subjects | APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CALCULATING CINEMATOGRAPHY COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS SEMICONDUCTOR DEVICES |
| title | VERIFYING METHOD FOR INTEGRATED CIRCUIT MASK PATTERN |
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