JPH059878B

The invention provides a semiconductor memory having a plurality of memory cells (12) and a bit line (BL1) connected to the memory cells (12), characterised by: the bit line (BL1) being formed of a plurality of sub-bit lines (BL1 a-c), switch means (11) for interconnecting and disconnecting the sub-bit lines (BL1 a-c), reference potential means (13) for storing reference potentials, and sense amplifier means (SA1-3) for comparing the output of an addressed memory cell (12) with the reference potentials, whereby the memory is capable of storing n-valued data using n different storage potentials.