METHOD FOR BIT PHASE SYNCHRONIZATION AND FRAME PHASE SYNCHRONIZATION

PURPOSE:To implement bit phase synchronization and frame phase synchronization while invalid data or a data delay in the frame phase synchronization is suppressed with simple configuration. CONSTITUTION:A byte just before a pointer in a reception frame (offset address #29) is detected by a #29 addre...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: ICHIMORI MINEKI, TAJIMA SEIJIRO, FUKAMI KENNOSUKE
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To implement bit phase synchronization and frame phase synchronization while invalid data or a data delay in the frame phase synchronization is suppressed with simple configuration. CONSTITUTION:A byte just before a pointer in a reception frame (offset address #29) is detected by a #29 address monitor section 4' and a reception pointer is loaded to a down-counter 8 when the byte is outputted from a bit synchronization buffer 1. The loading of the reception pointer to the down-counter 8 is delayed and the result of the delay is fetched for a time from the reception point of time of the xsi29 data (point of time when being written in the bit synchronization buffer 1) till the xsi29 data are outputted from a frame phase synchronization buffer 5. Furthermore, in the case of converting a transmission line phase fluctuation into a stuff, an active stuff byte is generated in the buffer and a position signal of a specific byte in which an absolute time location is fluctuated is used for a load timing to the down-counter 8 and the reception pointer is used for load data.