JPH0578944B

PURPOSE:To prevent the lowering of the operating frequency of a logic circuit by forming an N type diffusion layer in a Schottky-transistor region in which a Schottky-clamping type logic is formed on a low withstanding voltage section. CONSTITUTION:An N buried layer 2, an epitaxial growth layer 3, a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SHIMIZU ISAO, KANEKO KENJI, SATONAKA KOICHIRO, KIMURA MASATOSHI, OKABE TAKEAKI, KODA TOYOMASA, SAKAMOTO MITSUZO, HOYA KAZUO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To prevent the lowering of the operating frequency of a logic circuit by forming an N type diffusion layer in a Schottky-transistor region in which a Schottky-clamping type logic is formed on a low withstanding voltage section. CONSTITUTION:An N buried layer 2, an epitaxial growth layer 3, an isolation region 4, an N high-concentration impurity region, a P concentration impurity region 6, an insulating film 8 and an Al electrode are shaped on a semiconductor substrate 1. A diffusion layer 31 having depth in an extent that it is in contact with the arising of the N buried layer 2 in surface concentration of 10 - 10 cm of N type is introduced newly to the low withstanding voltage section epitaxial layer 3 forming a Schottky-transistor.