FAULT SIMULATION SYSTEM

PURPOSE:To reduce the memory capacity used in a fault simulation system which performs the fault simulation of a logic circuit including a RAM. CONSTITUTION:A test pattern deciding means 3 decides whether an input test pattern 2 is identical with an address fixed pattern or not based on the simulati...

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1. Verfasser: SEKINE YOSHIO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To reduce the memory capacity used in a fault simulation system which performs the fault simulation of a logic circuit including a RAM. CONSTITUTION:A test pattern deciding means 3 decides whether an input test pattern 2 is identical with an address fixed pattern or not based on the simulation model 1 of a logic circuit including the RAM and the pattern 2. If so, a model conversion means 5 produces a simulation model 6 by replacing the RAM of the model 1 with a latch circuit equivalent by one word. A fault simulation means 8 performs the fault simulation based on the model 6, the pattern 2, and a defined fault 7 and outputs a fault detection rate 9 and an output test pattern 10.