JPH055065B

PURPOSE:To enable continuous generation of a large number of patterns at a high speed, by providing an address memory section which enables simultaneous generation of the current address information and address information at the subsequent cycle when acessing a pattern memory section. CONSTITUTION:When accessed by an address outputted from a program counter 1, an address memory section 2 outputs a plurality of addresses for accessing a plurality of pattern memory sections 3 and 4 and an address for specifying the subsequent access position of a self-address memory section. Then, the address for specifying the subsequent access position of the self-address memory section outputted is set for the program counter 1 to make the address memory section 2 continuously generate addresses to access the pattern memory sections 3 and 4. In this manner, a series of pattern data read out by accessing the pattern memories 3 and 4 are outputted as integrated pattern data through a multiplexer mechanism comprising AND circuits 5 and 6, an inverter circuit 7 and an OR circuit 8.