MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To improve degree of freedom of transistor arrangement, cell internal wiring, etc., in an input/output basic cell by permitting a logical cell to be connected by metal wiring arranged on a first, second, third and more layers and arranging logical circuit power source wiring composed of the gate array on the first and the second layers. CONSTITUTION:Three or more logical circuit metal wiring layers composed of gate arrays are provided. For the metal wiring of an input/output basic cell, an input/output terminal 103 is connected with the input/output basic cell through metal wiring 108 arranged on the third metal wiring layer and the connecting via 110 of the wiring 108 and the input/output basic cell. The input/ output basic cell is connected with a basic cell area 102 through metal wiring 106 arranged on the third metal wiring layer and the connecting via 112 of the wiring 106 and the input/output basic cell. For a logical circuit constituted of the input/output cell, the input/output terminal 103 is arranged on the third metal wiring layer so as to be arranged on the input/output basic cell. Thus, the degree of freedom of the cell internal wiring, etc., is improved.