JPH05342846

PURPOSE:To attain an operational specification suited to a low speed and high speed use without attaining the high cost of a design or production or the like by integrating the low and high speed circuit parts which can be selectively operated by the setting from an outside in a buffer circuit constituting a digital input and output interface part, and selectively operating them. CONSTITUTION:At the time of setting an F/S signal to be 'H', a P-channel MOSTr M5 as a connection control circuit is turned off, a high speed circuit part 42 is not operated, a buffer circuit 4 is operated at a low speed and with a low power consumption only by a low speed circuit part 41. Next, at the time of setting the FS signal to be 'L', the Tr M5 is turned on, and the high speed circuit 42 is operated in parallel to the circuit part 41. Thus, operational specification suited to the high speed and low speed use can be arbitrarily selected and set by a register setting in an integrated circuit device, or the simple setting from the outside of the device.