JPH05335719
PURPOSE:To prevent dispersion of wiring interval and wiring ground caused by lowering of flatness of an insulation layer while ensuring configuration and size of a fine wiring line making a thickness of the insulation layer fixed and to reduce dispersion of electric characteristic. CONSTITUTION:An i...
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| creator | HATTORI HISAO YOSHINO KAN YAMANAKA SEISAKU IHARA HIROHIKO |
| description | PURPOSE:To prevent dispersion of wiring interval and wiring ground caused by lowering of flatness of an insulation layer while ensuring configuration and size of a fine wiring line making a thickness of the insulation layer fixed and to reduce dispersion of electric characteristic. CONSTITUTION:An insulation layer 2 is laminated on an insulation substrate 1 and wiring shape is engraved on the insulation layer 2 by exposure and development. After a metal layer 3 is formed thereon, a photoresist 4 thereon is removed. The process is repeated again and a two layer wiring substrate can be obtained. |
| format | Patent |
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CONSTITUTION:An insulation layer 2 is laminated on an insulation substrate 1 and wiring shape is engraved on the insulation layer 2 by exposure and development. After a metal layer 3 is formed thereon, a photoresist 4 thereon is removed. The process is repeated again and a two layer wiring substrate can be obtained.</description><edition>5</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>1993</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19931217&DB=EPODOC&CC=JP&NR=H05335719A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19931217&DB=EPODOC&CC=JP&NR=H05335719A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HATTORI HISAO</creatorcontrib><creatorcontrib>YOSHINO KAN</creatorcontrib><creatorcontrib>YAMANAKA SEISAKU</creatorcontrib><creatorcontrib>IHARA HIROHIKO</creatorcontrib><title>JPH05335719</title><description>PURPOSE:To prevent dispersion of wiring interval and wiring ground caused by lowering of flatness of an insulation layer while ensuring configuration and size of a fine wiring line making a thickness of the insulation layer fixed and to reduce dispersion of electric characteristic. CONSTITUTION:An insulation layer 2 is laminated on an insulation substrate 1 and wiring shape is engraved on the insulation layer 2 by exposure and development. After a metal layer 3 is formed thereon, a photoresist 4 thereon is removed. The process is repeated again and a two layer wiring substrate can be obtained.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1993</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD2CvAwMDU2NjU3tORhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFIOhyNiVEDAEARG7k</recordid><startdate>19931217</startdate><enddate>19931217</enddate><creator>HATTORI HISAO</creator><creator>YOSHINO KAN</creator><creator>YAMANAKA SEISAKU</creator><creator>IHARA HIROHIKO</creator><scope>EVB</scope></search><sort><creationdate>19931217</creationdate><title>JPH05335719</title><author>HATTORI HISAO ; YOSHINO KAN ; YAMANAKA SEISAKU ; IHARA HIROHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH05335719A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1993</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HATTORI HISAO</creatorcontrib><creatorcontrib>YOSHINO KAN</creatorcontrib><creatorcontrib>YAMANAKA SEISAKU</creatorcontrib><creatorcontrib>IHARA HIROHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HATTORI HISAO</au><au>YOSHINO KAN</au><au>YAMANAKA SEISAKU</au><au>IHARA HIROHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>JPH05335719</title><date>1993-12-17</date><risdate>1993</risdate><abstract>PURPOSE:To prevent dispersion of wiring interval and wiring ground caused by lowering of flatness of an insulation layer while ensuring configuration and size of a fine wiring line making a thickness of the insulation layer fixed and to reduce dispersion of electric characteristic. CONSTITUTION:An insulation layer 2 is laminated on an insulation substrate 1 and wiring shape is engraved on the insulation layer 2 by exposure and development. After a metal layer 3 is formed thereon, a photoresist 4 thereon is removed. The process is repeated again and a two layer wiring substrate can be obtained.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | JPH05335719 |
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