SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To reduce a difference generated in the output time of a data output buffer by controlling the activated time of the data output buffer in accordance with a distance between a power supply and ground. CONSTITUTION:When a control signal phin is turned to a high level, a data output buffer 0n...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: OYAMA JUNICHIRO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To reduce a difference generated in the output time of a data output buffer by controlling the activated time of the data output buffer in accordance with a distance between a power supply and ground. CONSTITUTION:When a control signal phin is turned to a high level, a data output buffer 0n is turned to an activated state, and when a gate signal phi0n exceeds a theshold voltage, a transistor(TR) n3 is turned on and a data output signal phiDn starts to rise from a HigH-Z level. The final data output buffer 01 is turned to the activated state by successively executing similar operation. Since the sizes of TRs 11 to n1 for driving respective data output TRs 13 to n3 are W11>=W21>=->=Wn1, the rising speeds of gate signals phi01 to phi0n are phi01 to phi0n in a descending order. On the other hand, the rising speeds of the data output buffer control signals phi1 to phin are phin-1 to phi1 in the descending order due to delay inverters.