JPH05308570

PURPOSE: To exactly generate a vertical reset pulse irrespective of the phase of Vsync and a delay set value for vertical reset. CONSTITUTION: A comparator 1103 compares the output of a counter 1101 with a delay set value corresponding to a desired pan value, and when they are coincident, it outputs...

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Hauptverfasser:	KAARU FURANSHISU HORANDAA, TEIMOSHII UIRIAMU SHIIGAA
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY PICTORIAL COMMUNICATION, e.g. TELEVISION
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creator	KAARU FURANSHISU HORANDAA TEIMOSHII UIRIAMU SHIIGAA
description	PURPOSE: To exactly generate a vertical reset pulse irrespective of the phase of Vsync and a delay set value for vertical reset. CONSTITUTION: A comparator 1103 compares the output of a counter 1101 with a delay set value corresponding to a desired pan value, and when they are coincident, it outputs a start reset signal Str- Rst. A circuit including flip flops 1108 and 1110 generates a first signal for starting a delayed reset pulse based on the Str- Rst. A circuit including flip flops 1102, 1104, and 1106 generates a second signal for starting the delayed reset pulse based on Vsync. A circuit including a flip flop 1112, AND gate 1116, and NOR gate 1120 outputs the first signal when it is present, and outputs the second signal when the first signal is not present. A counter 1114 generates a vertical reset pulse Vrst based on this output.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH05308570A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH05308570A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH05308570A3</originalsourceid><addsrcrecordid>eNrjZOD2CvAwMDU2sDA1N-BhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFIOhyNiVEDAD1_G6o</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>JPH05308570</title><source>esp@cenet</source><creator>KAARU FURANSHISU HORANDAA ; TEIMOSHII UIRIAMU SHIIGAA</creator><creatorcontrib>KAARU FURANSHISU HORANDAA ; TEIMOSHII UIRIAMU SHIIGAA</creatorcontrib><description>PURPOSE: To exactly generate a vertical reset pulse irrespective of the phase of Vsync and a delay set value for vertical reset. CONSTITUTION: A comparator 1103 compares the output of a counter 1101 with a delay set value corresponding to a desired pan value, and when they are coincident, it outputs a start reset signal Str- Rst. A circuit including flip flops 1108 and 1110 generates a first signal for starting a delayed reset pulse based on the Str- Rst. A circuit including flip flops 1102, 1104, and 1106 generates a second signal for starting the delayed reset pulse based on Vsync. A circuit including a flip flop 1112, AND gate 1116, and NOR gate 1120 outputs the first signal when it is present, and outputs the second signal when the first signal is not present. A counter 1114 generates a vertical reset pulse Vrst based on this output.</description><edition>5</edition><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><creationdate>1993</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19931119&DB=EPODOC&CC=JP&NR=H05308570A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19931119&DB=EPODOC&CC=JP&NR=H05308570A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KAARU FURANSHISU HORANDAA</creatorcontrib><creatorcontrib>TEIMOSHII UIRIAMU SHIIGAA</creatorcontrib><title>JPH05308570</title><description>PURPOSE: To exactly generate a vertical reset pulse irrespective of the phase of Vsync and a delay set value for vertical reset. CONSTITUTION: A comparator 1103 compares the output of a counter 1101 with a delay set value corresponding to a desired pan value, and when they are coincident, it outputs a start reset signal Str- Rst. A circuit including flip flops 1108 and 1110 generates a first signal for starting a delayed reset pulse based on the Str- Rst. A circuit including flip flops 1102, 1104, and 1106 generates a second signal for starting the delayed reset pulse based on Vsync. A circuit including a flip flop 1112, AND gate 1116, and NOR gate 1120 outputs the first signal when it is present, and outputs the second signal when the first signal is not present. A counter 1114 generates a vertical reset pulse Vrst based on this output.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1993</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD2CvAwMDU2sDA1N-BhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFIOhyNiVEDAD1_G6o</recordid><startdate>19931119</startdate><enddate>19931119</enddate><creator>KAARU FURANSHISU HORANDAA</creator><creator>TEIMOSHII UIRIAMU SHIIGAA</creator><scope>EVB</scope></search><sort><creationdate>19931119</creationdate><title>JPH05308570</title><author>KAARU FURANSHISU HORANDAA ; TEIMOSHII UIRIAMU SHIIGAA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH05308570A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1993</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><toplevel>online_resources</toplevel><creatorcontrib>KAARU FURANSHISU HORANDAA</creatorcontrib><creatorcontrib>TEIMOSHII UIRIAMU SHIIGAA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KAARU FURANSHISU HORANDAA</au><au>TEIMOSHII UIRIAMU SHIIGAA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>JPH05308570</title><date>1993-11-19</date><risdate>1993</risdate><abstract>PURPOSE: To exactly generate a vertical reset pulse irrespective of the phase of Vsync and a delay set value for vertical reset. CONSTITUTION: A comparator 1103 compares the output of a counter 1101 with a delay set value corresponding to a desired pan value, and when they are coincident, it outputs a start reset signal Str- Rst. A circuit including flip flops 1108 and 1110 generates a first signal for starting a delayed reset pulse based on the Str- Rst. A circuit including flip flops 1102, 1104, and 1106 generates a second signal for starting the delayed reset pulse based on Vsync. A circuit including a flip flop 1112, AND gate 1116, and NOR gate 1120 outputs the first signal when it is present, and outputs the second signal when the first signal is not present. A counter 1114 generates a vertical reset pulse Vrst based on this output.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record>
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subjects	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY PICTORIAL COMMUNICATION, e.g. TELEVISION
title	JPH05308570
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T18%3A58%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KAARU%20FURANSHISU%20HORANDAA&rft.date=1993-11-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH05308570A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true