JPH05308570

PURPOSE: To exactly generate a vertical reset pulse irrespective of the phase of Vsync and a delay set value for vertical reset. CONSTITUTION: A comparator 1103 compares the output of a counter 1101 with a delay set value corresponding to a desired pan value, and when they are coincident, it outputs a start reset signal Str- Rst. A circuit including flip flops 1108 and 1110 generates a first signal for starting a delayed reset pulse based on the Str- Rst. A circuit including flip flops 1102, 1104, and 1106 generates a second signal for starting the delayed reset pulse based on Vsync. A circuit including a flip flop 1112, AND gate 1116, and NOR gate 1120 outputs the first signal when it is present, and outputs the second signal when the first signal is not present. A counter 1114 generates a vertical reset pulse Vrst based on this output.