JPH05289947

PURPOSE:To attain high-speed data transfer between a main storage and a buffer storage without lossing reliability by suppressing ECC check for continuous data transfer between the main storage and the buffer storage. CONSTITUTION:At the time of continuous data transfer between the main storage 3 and the buffer storage 2, an ECC checking & correcting circuit 9 is suppressed to execute high-speed data transfer. The address of the initial 1-bit error generated at the time of continuous data transfer and corrected data are inputted to a register, and after completing the data transfer, data in the main storage 3 and the buffer storage 2 specified by the address stored in the register are rewitten by the data of the register. Thus the block address of the 1-bit error generated at first at the time of continuous data transfer is inputted to the register, and after completing the data transfer, CC check is applied to all data of the block specified by the register. When a 1-bit error is generated, corrected data are written in both the storages 3, 2.