JPH05250309

PURPOSE:To decrease the traffic of a 32-bit bus by efficiently connecting a 16-bit bus and the 32-bit bus which differ in bit width. CONSTITUTION:A processor 3 and a main memory 4 are connected to the 16-bit bus 2 and an extended memory 8 is connected to the 32-bit bus 7. The 16-bit bus 2 transfers address data in one cycle and the 32-bit bus 7 transfers data in a sequence of several cycles with a command. A buffer control circuit 11 monitors requests and addresses inputted from the 16-bit bus 2 and when the same requests are sent to successive addresses, those requests are stored in a request register 6 and outputted as one request to the 32-bit bus 7. The buffer control circuit 11, on the other hand, inputs 32-bit width data from the 32-bit bus 7 to a response register 9, and divides the data in conformity with the 16-bit bus 2 and outputs them.