JPH05250156

PURPOSE:To increase the processing speed by adding the value of address low- order bits and the value of address high-order bits held by an address high-order bit holding register and outputting the result as address data. CONSTITUTION:An instruction decoder 2 decodes a sent 'instruction 1', indicates the execution of mathematical arithmetic to a mathematical arithmetic part 4, and takes a value to be set from the 'instruction 1' and sends it to the mathematical arithmetic part 4 and address high-order bit holding register 10, so that the value is set. Further, the instruction decoder 2 decodes a next 'instruction 2', indicates address calculation to an address generation part 3, and sends the value of the address high-order bits from the address high-order bit holding register 10 to the address generation part 3. Further, the value of the address low-order bits to be added to the address high-order bits is taken out of the 'instruction 2' and sent to the address generation part 3. The address generation part 3 adds the values of those address high-order bits and address low-order bits together.