JPH05250066

PURPOSE:To generate a clock signal having an arbitrary duty ratio from a frequency higher than a basic clock frequency to a lower frequency. CONSTITUTION:This circuit is provided with a control register 5 to store the frequency of the desired clock signal to be outputted and the value of the duty ratio and to output that value, data conversion part 6 to convert the output of the control register 5 into a prescribed bit sequence and to output it, and memory part 4 to store the output of the data conversion part 6 and to store it from the inputted address value to an M-th address. Synchronously to the output signal of a basic clock oscillator 1, data from the address to the M-th address in the memory part 4 designated by an address counter 2 to output the address value are read by a data serializer 7A or 7B designated by a serializer control signal alternately designated by a serializer control circuit 16, and the clock signal is outputted synchronously to the output of a synchronizing signal oscillator 18 from the data serializer 7A or 7B designated by an output control signal generator 17.