JPH05242048

PURPOSE:To simply and inexpensively construct the device by constituting it so that a bus request cannot be outputted, when other processor is outputting a bus request signal, or a system bus is being used and a busy signal is asserted. CONSTITUTION:When an arithmetic processing part 74 gives a request for using a bus to a bus request obtaining circuit 71, the circuit 71 asserts a bus request signal. A processor always monitors bus signals B and C through input buffer circuits 76a, 76b, and asserts a signal 81 by a NAND circuit 78c, in the case when signals of both of them are both inactive. When this signal 81 is active, and a bus request signal 82 of the bus request obtaining circuit is active, an internal bus request is given to a signal 84. However, even if a busy signal of the bus is inactive, in the case when other processor is outputting a bus request, the signal 81 becomes active, and the bus request signal 84 does not become active.