JPH05242026

PURPOSE:To execute a data transfer processing between a host device and a secondary storage device at a high speed. CONSTITUTION:In host devices 1, 2, clock selecting circuits 6, 7 and data transfer circuits 8, 9 are contained, respectively. When the host device 1 or 2 executes a data transfer to a secondary storage device 3, 4 or 5, a clock of the highest speed is selected by a clock selecting circuit 6 or 7 in accordance with the highest transfer speed of the secondary storage device which becomes an object, and the selected clock is supplied to the secondary storage device through a transfer clock signal line 13. Transfer data is synchronized with the selected clock, transferred through a data storage circuit 8 or 9 and a data transfer signal line 14, and given and received to and from the secondary storage device. In the secondary storage devices 3, 4 and 5, data is given and received in accordance with the supplied clock by data transfer circuits 10, 11 or 12. Accordingly, at the time of data transfer, the data transfer can be executed at a high speed by selecting the clock of the highest speed of the secondary storage device being the other party of the data transfer.