SEMICONDUCTOR DEVICE

PURPOSE:To decrease a leak current, and also to reduce the variation of the threshold voltage of a MOS by a method wherein the gate length of the gate electrode on the boundary region between an active region and an inactive region is formed longer than the gate length of the gate electrode length o...

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Bibliographische Detailangaben
Hauptverfasser: YASUI KIYOSHI, YASUOKA HIDEKI, NAGAI HIROAKI, KODA TOYOMASA
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To decrease a leak current, and also to reduce the variation of the threshold voltage of a MOS by a method wherein the gate length of the gate electrode on the boundary region between an active region and an inactive region is formed longer than the gate length of the gate electrode length of the active region. CONSTITUTION:In the boundary region between the end part of an interelement isolation insulating film 6, i.e., an active region and a non-active region, the gate length of a gate electrode 9 is longer than the gate length of the gate electrode 9 on the active region. Consequently, as the distance between two n-type semiconductor 10 becomes larger, the length of leak path due to crystal defect becomes long. Accordingly, the leak current applied through the leak path is decreased. Also, as the distance between the two n-type semiconductor regions becomes longer, an inverted layer is hardly formed between the n-type semiconductor regions, and the variation of the threshold voltage of a MISFETQ can be lessened. As a result, the performance characteristics of the semiconductor device can be improved.