TEST SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR DEVICE

PURPOSE:To obtain a test signal generation circuit of a semiconductor device which a conventional external input pin to be used and a test signal to be generated without applying a high voltage to this external input pin. CONSTITUTION:A short-pulse control signal with a different cycle from the specified cycle is inserted into an external clock signal phi1 at times t6 and t8 at test operation. In this case, when the external clock signal phi1 becomes low at the time t6, an NOR circuit 3 performs NOR operation between an output signal b of an inverter 2 and the external clock signal phi1 so that an output signal c of the NOR circuit 3 becomes high at a time t7. Then, when the external clock phi1 becomes high at the time t8, a D-type flip-flop 4 latches a high level of an output signal c of the NOR circuit 3 so that an output of the D-type flip-flop stays high at the time t9, thus enabling a high-level test signal to be supplied to a test circuit of a semiconductor device.