INTEGRATED CIRCUIT CHIP-PACKAGE STRUCTURE

INTEGRATED CIRCUIT CHIP-PACKAGE STRUCTURE

PURPOSE: To reduce capacitance of signal line, related to a multi-layer integrated circuit chip package structure comprising a reference conductive layer and a patterned conductive layer comprising, while adjoining the reference conductive layer, a narrow signal line and a wide signal line is assign...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: PERUWAITSU NIHARU, HENRII DAINIRU SHIYUNAAMAN, BURUHAN OZUMATSUTO, AASAA RICHIYAADO JINGAA, SUKOTSUTO ROORENSU YAKOBUSU
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:PURPOSE: To reduce capacitance of signal line, related to a multi-layer integrated circuit chip package structure comprising a reference conductive layer and a patterned conductive layer comprising, while adjoining the reference conductive layer, a narrow signal line and a wide signal line is assigned. CONSTITUTION: An integrated circuit chip package comprises a reference conductive layer 8, which supplies a voltage for electric power or earth and a patterned conductive layer which, assigned adjoining it, comprises a narrow signal line 20 and a wide signal line 19. The reference conductive layer 8 of a region 7 facing the wide signal line 19 is removed, so that no layer is present in the region. Thus, the capacitance of the signal line is reduced for optimum operation.