INSPECTING APPARATUS

PURPOSE:To reduce a period of time from decision to completion of a failure analysis of a semiconductor integrated circuit device. CONSTITUTION:An inspection apparatus is equipped with a combined jig for LSI packaging purposes 6 which can be used for the test of an LSI 8 by an LSI tester 2, and can...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	SUZUKI HIROSHI, NISHIOKA HISASHI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	PURPOSE:To reduce a period of time from decision to completion of a failure analysis of a semiconductor integrated circuit device. CONSTITUTION:An inspection apparatus is equipped with a combined jig for LSI packaging purposes 6 which can be used for the test of an LSI 8 by an LSI tester 2, and can also be used for the failure analysis of the LSI 8 by an EB tester 7. The combined jig 6 enables a drive signal to flow from the LSI tester 2 to the LSI 8, and enables an output signal to flow from the LSI 8 to the LSI tester 2 when the LSI 8 is tested by the LSI tester 2. When the LSI 8 undergoes a failure analysis by means of the EB tester T, the combined jig 6 is fitted to a vacuum processing chamber port 7a, so that a vacuum processing chamber is constituted. Also, the jig can assure a vacuum state in the chamber.