POWER SYSTEM PROTECTION SYSTEM

PURPOSE:To achieve control with a simple algorithm and enable time required for function recovery of system to be reduced by detecting a data error which is generated due to a transmission path fault and a device fault according to a reception data and then controlling a bit which indicates validity...

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1. Verfasser: HIKITA TAKEO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To achieve control with a simple algorithm and enable time required for function recovery of system to be reduced by detecting a data error which is generated due to a transmission path fault and a device fault according to a reception data and then controlling a bit which indicates validity of a frame whose data error is detected and then transmitting the frame. CONSTITUTION:A ready bit control circuit 30 of a transmission part 4 operates in synchronization with a timing signal 31 of a counter 7b, thus enabling a ready bit 26 of a frame to be controlled based on various kinds of control conditions. Then, when a data which is transmitted from a reception part 3 in synchronization with a timing signal 9b is a frame for another terminal, a data transmission control part 12b transmits it as it is, multiplexes a current data for its own terminal if it is a frame for its own terminal, multiplexes the ready bit 26 from the ready bit control part 30 at each frame, and then transmits a transmission data 5t to a downstream relay device, thus enabling all relay devices on a transmission loop to receive transmission failure information normally.