MEMORY CIRCUIT SYSTEM

PURPOSE:To obtain a memory circuit system to prevent useless access to a main storage device by advancing automatically the read address of the main storage device when a hit arises in a cache memory. CONSTITUTION:In a memory circuit, the cache memory 2 is provided for the main storage device 1, and...

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Bibliographische Detailangaben
Hauptverfasser: NAGABORI KAZUO, TANIHIRA HISAMITSU
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To obtain a memory circuit system to prevent useless access to a main storage device by advancing automatically the read address of the main storage device when a hit arises in a cache memory. CONSTITUTION:In a memory circuit, the cache memory 2 is provided for the main storage device 1, and read-out is executed by giving an address in parallel. In this case, a memory control circuit 3 is provided, and when hit information is received from the cache memory 2, the address is advanced by the equivalent of read-out block length in the cache memory 2, and the read-out is executed from the main storage device 1 by this. At that time, in order that the read-out is executed from the main storage device 1 by advancing the address, a (+1) circuit 4 is provided in the memory control circuit 3, and a CAS address is advanced by one block, and the CAS address or the output of the (+1) circuit 4 is selected by a selector 5 in accordance with the hit information, and is given to the main storage device 1.