JPH0510873B

PURPOSE:To obtain a scanning speed converting circuit with a small memory capacity by allowing a memory circuit to write one picture element and to read plural picture elements alternately, and outputting a picture signal subjected to speed conversion in a period of plural times. CONSTITUTION:A picture signal from a terminal 1 is fed to picture element memories 20-23 in common via a buffer circuit 19 and a switching circuit 24. An input/output control circuit 18 generates a prescribed control signal by using an R/W signal and a clock signal supplied from a signal line 17. A decoder circuit 25 outputs a drive clock signal driving only one picture element memory of the memories 20-23 with an address signal inputted from the signal path 16 and a part of the control signal. On the other hand, when the R/W signal reaches the write state, only one picture element memory is driven by the drive clock, the stored picture signal is read and fed to an output detection circuit 26. The circuit 26 stores the read picture signal to a picture element memory via the circuit 24 and supplied it to a buffer circuit 27 and a reproduced picture is outputted to a terminal 3.