CACHE MEMORY CONTROL SYSTEM

PURPOSE:To prevent system-down caused by a parity error by comparing an output of a cache management table, and a part of an address signal from a processor and its parity code, and executing a cache hit/cache mishit processing. CONSTITUTION:A cache management table 2 inputs a second part (m+1 to n bit part) used for accessing it, and outputs information (m+1 bit length) corresponding thereto and a parity code (p) thereby. A comparing circuit 13 compares a prescribed output of a processor and an output of the cache management table 2. That is, a first signal consisting of a first part (0 to m bit part) and a parity code p' outputted from the processor, and a second signal consisting of the information (m+1 bit length) of the output of the cache management table 2 and the parity code (p) are compared, and in the case a second signal is a signal for generating a parity error, a fact that a first signal and a second signal do not coincide with each other is outputted.