BUS ARBITRATION SYSTEM

PURPOSE:To shorten the access time and to improve the throughout of a CPU by providing a DMA mode detecting means which detects whether or not a DMA controller is in process of device transfer in response to a CPU's indication. CONSTITUTION:The DMA mode detecting means 5 monitors DMA transfer request signals 8 - 9 for DMA controllers 2 - 3 from the CPU 1 at all times and sends their OR output as a DMA mode indication signal 10 to the CPU 1 and a system bus arbitrating circuit 6. The DMA transfer request signals 8 - 9 become '1' when the CPU 1 sends a DMA transfer request and become '0' when end information from each DMA controller is received. Then when the DMA mode indication signal 10 is outputted and becomes '1', the system bus arbitrating circuit 6 arbitrates a bus and the CPU 1 also sends a bus use request signal 11 to the system bus arbitrating circuit 6. Consequently, the access time is shortened and the throughout of the CPU is improved.