SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF

PURPOSE:To enhance the yield of a semiconductor integrated circuit device by providing a structure in which the grounded-emitter current-amplification factor (h) of a bipolar transistor is nearly definite in a low-current region (withing a range where a collector current is 1 [nA] to 100[muA]). CONS...

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Bibliographische Detailangaben
Hauptverfasser: KURAMOTO TADASHI, KUDO SATOSHI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To enhance the yield of a semiconductor integrated circuit device by providing a structure in which the grounded-emitter current-amplification factor (h) of a bipolar transistor is nearly definite in a low-current region (withing a range where a collector current is 1 [nA] to 100[muA]). CONSTITUTION:An insulating film 25 is constituted of a thermal silicon oxide film formed by a thermal oxidation method; and the film 25 comes into direct contact with respective main faces of a p-type semiconductor region 27 and a p type semiconductor region 31. When an insulating film which does not contain or has a reduced high-melting-point metal or high-melting-point silicide metal in the film 25 is used, a surface recombination is reduced in a base region. As a result, it is possible to reduce a drop in the increase amount of a collector current against a base current. That is to say, since a grounded-emitter current- amplification factor (hFE) can be made nearly definite in the low-current region, the defect rate at a characteristic test can be reduced and the yield of a Bi- CMOS can be enhanced.