JPH0472269B

PURPOSE:To improve the speed of logical simulation by dividing a logical circuit into logical function units and registering an input and an output value in a memory, and usng said registered values and omit arithmetic process when the same logical value input is necessary. CONSTITUTION:Logical func...

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1. Verfasser:	ONIZUKA NOBUHIKO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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creator	ONIZUKA NOBUHIKO
description	PURPOSE:To improve the speed of logical simulation by dividing a logical circuit into logical function units and registering an input and an output value in a memory, and usng said registered values and omit arithmetic process when the same logical value input is necessary. CONSTITUTION:Logical functions are stored in a function logical file (FLF)5 as proper units while described by employing a loop system, truth table, etc. A gate logical file (GLF)6 is generated automatically through a conversion program by inputting the FLF5. Information and simulation data 2 described in the FLF5 and GLF6 are inputted to perform simulation, whose result 3 is outputted. Inputs and outputs are registered in the FLF5 as to each divided function unit of the logical circuit, and arithmetic is omitted for the same input to use the corresponding registered output. Thus, the speed of the simulation is increased.
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CONSTITUTION:Logical functions are stored in a function logical file (FLF)5 as proper units while described by employing a loop system, truth table, etc. A gate logical file (GLF)6 is generated automatically through a conversion program by inputting the FLF5. Information and simulation data 2 described in the FLF5 and GLF6 are inputted to perform simulation, whose result 3 is outputted. Inputs and outputs are registered in the FLF5 as to each divided function unit of the logical circuit, and arithmetic is omitted for the same input to use the corresponding registered output. Thus, the speed of the simulation is increased.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19921117&DB=EPODOC&CC=JP&NR=H0472269B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19921117&DB=EPODOC&CC=JP&NR=H0472269B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ONIZUKA NOBUHIKO</creatorcontrib><title>JPH0472269B</title><description>PURPOSE:To improve the speed of logical simulation by dividing a logical circuit into logical function units and registering an input and an output value in a memory, and usng said registered values and omit arithmetic process when the same logical value input is necessary. CONSTITUTION:Logical functions are stored in a function logical file (FLF)5 as proper units while described by employing a loop system, truth table, etc. A gate logical file (GLF)6 is generated automatically through a conversion program by inputting the FLF5. Information and simulation data 2 described in the FLF5 and GLF6 are inputted to perform simulation, whose result 3 is outputted. Inputs and outputs are registered in the FLF5 as to each divided function unit of the logical circuit, and arithmetic is omitted for the same input to use the corresponding registered output. Thus, the speed of the simulation is increased.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD2CvAwMDE3MjKzdOJhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFIOpyMjIlSBAB9ThxO</recordid><startdate>19921117</startdate><enddate>19921117</enddate><creator>ONIZUKA NOBUHIKO</creator><scope>EVB</scope></search><sort><creationdate>19921117</creationdate><title>JPH0472269B</title><author>ONIZUKA NOBUHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH0472269BB23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1992</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>ONIZUKA NOBUHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ONIZUKA NOBUHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>JPH0472269B</title><date>1992-11-17</date><risdate>1992</risdate><abstract>PURPOSE:To improve the speed of logical simulation by dividing a logical circuit into logical function units and registering an input and an output value in a memory, and usng said registered values and omit arithmetic process when the same logical value input is necessary. CONSTITUTION:Logical functions are stored in a function logical file (FLF)5 as proper units while described by employing a loop system, truth table, etc. A gate logical file (GLF)6 is generated automatically through a conversion program by inputting the FLF5. Information and simulation data 2 described in the FLF5 and GLF6 are inputted to perform simulation, whose result 3 is outputted. Inputs and outputs are registered in the FLF5 as to each divided function unit of the logical circuit, and arithmetic is omitted for the same input to use the corresponding registered output. Thus, the speed of the simulation is increased.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
title	JPH0472269B
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