SEMICONDUCTOR MEMORY DEVICE

PURPOSE:To make one of polycrystalline silicon wirings which serve as a gate electrode small in gap so as to make a chip small in size by a method wherein the drain electrode of a MOS transistor is connected to a bit line through a contact hole and an impurity diffusion layer which is opposite to a...

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1. Verfasser: CHATANI SHIGEO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To make one of polycrystalline silicon wirings which serve as a gate electrode small in gap so as to make a chip small in size by a method wherein the drain electrode of a MOS transistor is connected to a bit line through a contact hole and an impurity diffusion layer which is opposite to a semiconductor substrate in conductivity type and diffused through the contact hole concerned. CONSTITUTION:Only a part of an N-type diffusion layer 28 serving as a drain electrode is located under a contact hole 29. N-type diffusion layers 28 and 32 are connected together and a bit line 25 and a drain electrode are also connected together through the N-type diffusion layer 32 diffused through a contact hole 29. Polycrystalline silicon wirings 26 which serve as the gate electrode of a MOS transistor and a word line are required to be large in gap when the contact hole 29 is located only at a cell on one side of the bit line 25, and the size L' of the gap can be reduced by the size of a contact hole and an overlap margin of the contact hole 29 and the N-type diffusion layer 28, so that a chip can be miniaturized.