JPH0467338B

PURPOSE:To readily perform high speed and low power consumption of a hetero junction type FET by introducing doner impurity into the depth which reaches an electron storage layer from the surface of a semiconductor layer having a film selectively covered and then forming an electrode which ohmically...

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1. Verfasser: KOTANI KOICHIRO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To readily perform high speed and low power consumption of a hetero junction type FET by introducing doner impurity into the depth which reaches an electron storage layer from the surface of a semiconductor layer having a film selectively covered and then forming an electrode which ohmically contacts the third semiconductor layer in the region having no film. CONSTITUTION:A non-doped GaAs layer 12, an N type layer AlGaAs layer 13 and an N type GaAs layer 14 are sequentially epitaxially grown on a semi- insulating GaAs substrate 11. The layer 13 becomes an electron supplying layer, electrons are transferred to the layer 12, and an electron storage layer 15 is formed in the vicinity of the hetero junction between both layers in the layer 12. Then, a protective film 16 which covers the layer 14 is formed, and high density doner impurity is implanted to the region on which source and drain electrodes forming ohmic contact with the semiconductor substrate are arranged and to the region on which the gate electrode of the depletion mode is arranged. Silicon is used as doner impurity. Then, an ion implanted mask 17 is removed, a protective film 20 is formed, and a heat treatment is performed, thereby activating the implanted ions.