INTERFACE CONTROL CIRCUIT

PURPOSE:To improve the availability of a CPU by producing an interruption signal to the CPU only when the data held by a holding means holding successively the data reaches a prescribed amount and reading out and processing the held data by the CPU in response to the interruption signal. CONSTITUTION:When the data held by a holding means 4 or 5 reaches a prescribed amount, a timing control circuit 3 produces an interruption signal to a data processor CPU 6. Then the CPU 6 reads out continuously the held data in response to the interruption signal. That is, the FIFO 4 and 5 are provided in an interface circuit and the data are continuously read out for each fixed unit after detecting the saturated states of both FIFOs. Thus the overhead time is shortened for the interruption processing of the CPU 6 and the performance of the CPU 6 is apparently improved.