JPH0457108B

PURPOSE:To reduce the pad area required for inter-chip connection by a method wherein inter-chip connections are formed on both surfaces of a contact film by alternate lamination of a plurality semiconductor chips and flexible, insulating contact films. CONSTITUTION:The first layer chips 12A-12C are...

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1. Verfasser: TANIZAWA SATORU
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To reduce the pad area required for inter-chip connection by a method wherein inter-chip connections are formed on both surfaces of a contact film by alternate lamination of a plurality semiconductor chips and flexible, insulating contact films. CONSTITUTION:The first layer chips 12A-12C are die-bonded on a stage 11 of large thermal conductivity, and the first layer contact film 14 is put thereon; then, conductive patterns 15 on the bottom of the film 14 are bonded to bonding pads 13A-13C of the chips 12A-12C. Conductive patterns 16 are formed on the top of the film 14, and the respective patterns 15, 16 are connected by forming Via 17A-17C in position. The second layer chip 18 is put on, and the second layer contact film 20 is put thereon. Bonding pads 19 of the chip 18, patterns 16, and conductive patterns 21 on the bottom of the film 20 are bonded. Finally, the third layer contact film 26 and the third layer chip 24 are formed in the same manner, thus reducing the pad area.