ADDRESS CONVERSION CIRCUIT
PURPOSE:To reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI by switching the enable timing between a counter which outputs the higher rank bits of an address and a counter which outputs the lower rank bits and pe...
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| creator | ICHIKAWA TAKUYA EGUCHI KATSUHIRO |
| description | PURPOSE:To reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI by switching the enable timing between a counter which outputs the higher rank bits of an address and a counter which outputs the lower rank bits and performing the vertical/horizontal conversion of the address. CONSTITUTION:The 1st and 2nd counters 1 and 2 produce the circulation higher and lower rank addresses in their own enable states, and the 1st and 2nd selectors 3 and 4 output the enable signals to the counters 1 and 2 respectively. A decoding/switching means 5 detects a fact that the outputs of both counters 1 and 2 reach each maximum level and performs the switching of selections via the selectors 3 and 4. One of both selectors 3 and 4 always selects an enable signal and the other selector selects the ripple carry output between both selectors. Thus it is possible to reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI. |
| format | Patent |
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CONSTITUTION:The 1st and 2nd counters 1 and 2 produce the circulation higher and lower rank addresses in their own enable states, and the 1st and 2nd selectors 3 and 4 output the enable signals to the counters 1 and 2 respectively. A decoding/switching means 5 detects a fact that the outputs of both counters 1 and 2 reach each maximum level and performs the switching of selections via the selectors 3 and 4. One of both selectors 3 and 4 always selects an enable signal and the other selector selects the ripple carry output between both selectors. Thus it is possible to reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI.</description><language>eng</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; CALCULATING ; COMPUTING ; COUNTING ; CRYPTOGRAPHY ; DISPLAY ; EDUCATION ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; PHYSICS ; PICTORIAL COMMUNICATION, e.g. TELEVISION ; SEALS</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19920207&DB=EPODOC&CC=JP&NR=H0437934A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19920207&DB=EPODOC&CC=JP&NR=H0437934A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ICHIKAWA TAKUYA</creatorcontrib><creatorcontrib>EGUCHI KATSUHIRO</creatorcontrib><title>ADDRESS CONVERSION CIRCUIT</title><description>PURPOSE:To reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI by switching the enable timing between a counter which outputs the higher rank bits of an address and a counter which outputs the lower rank bits and performing the vertical/horizontal conversion of the address. CONSTITUTION:The 1st and 2nd counters 1 and 2 produce the circulation higher and lower rank addresses in their own enable states, and the 1st and 2nd selectors 3 and 4 output the enable signals to the counters 1 and 2 respectively. A decoding/switching means 5 detects a fact that the outputs of both counters 1 and 2 reach each maximum level and performs the switching of selections via the selectors 3 and 4. One of both selectors 3 and 4 always selects an enable signal and the other selector selects the ripple carry output between both selectors. Thus it is possible to reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI.</description><subject>ADVERTISING</subject><subject>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>CRYPTOGRAPHY</subject><subject>DISPLAY</subject><subject>EDUCATION</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</subject><subject>PHYSICS</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><subject>SEALS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJBydHEJcg0OVnD29wtzDQr29PdTcPYMcg71DOFhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GJsbmlsYmjsZEKAEACBogPA</recordid><startdate>19920207</startdate><enddate>19920207</enddate><creator>ICHIKAWA TAKUYA</creator><creator>EGUCHI KATSUHIRO</creator><scope>EVB</scope></search><sort><creationdate>19920207</creationdate><title>ADDRESS CONVERSION CIRCUIT</title><author>ICHIKAWA TAKUYA ; EGUCHI KATSUHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH0437934A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1992</creationdate><topic>ADVERTISING</topic><topic>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>CRYPTOGRAPHY</topic><topic>DISPLAY</topic><topic>EDUCATION</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</topic><topic>PHYSICS</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><topic>SEALS</topic><toplevel>online_resources</toplevel><creatorcontrib>ICHIKAWA TAKUYA</creatorcontrib><creatorcontrib>EGUCHI KATSUHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ICHIKAWA TAKUYA</au><au>EGUCHI KATSUHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ADDRESS CONVERSION CIRCUIT</title><date>1992-02-07</date><risdate>1992</risdate><abstract>PURPOSE:To reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI by switching the enable timing between a counter which outputs the higher rank bits of an address and a counter which outputs the lower rank bits and performing the vertical/horizontal conversion of the address. CONSTITUTION:The 1st and 2nd counters 1 and 2 produce the circulation higher and lower rank addresses in their own enable states, and the 1st and 2nd selectors 3 and 4 output the enable signals to the counters 1 and 2 respectively. A decoding/switching means 5 detects a fact that the outputs of both counters 1 and 2 reach each maximum level and performs the switching of selections via the selectors 3 and 4. One of both selectors 3 and 4 always selects an enable signal and the other selector selects the ripple carry output between both selectors. Thus it is possible to reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
| recordid | cdi_epo_espacenet_JPH0437934A |
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| subjects | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CALCULATING COMPUTING COUNTING CRYPTOGRAPHY DISPLAY EDUCATION ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS PICTORIAL COMMUNICATION, e.g. TELEVISION SEALS |
| title | ADDRESS CONVERSION CIRCUIT |
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