ADDRESS CONVERSION CIRCUIT

PURPOSE:To reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI by switching the enable timing between a counter which outputs the higher rank bits of an address and a counter which outputs the lower rank bits and pe...

Ausführliche Beschreibung

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Hauptverfasser: ICHIKAWA TAKUYA, EGUCHI KATSUHIRO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI by switching the enable timing between a counter which outputs the higher rank bits of an address and a counter which outputs the lower rank bits and performing the vertical/horizontal conversion of the address. CONSTITUTION:The 1st and 2nd counters 1 and 2 produce the circulation higher and lower rank addresses in their own enable states, and the 1st and 2nd selectors 3 and 4 output the enable signals to the counters 1 and 2 respectively. A decoding/switching means 5 detects a fact that the outputs of both counters 1 and 2 reach each maximum level and performs the switching of selections via the selectors 3 and 4. One of both selectors 3 and 4 always selects an enable signal and the other selector selects the ripple carry output between both selectors. Thus it is possible to reduce the power consumption and the packing area and also to facilitate the transformation of an address conversion circuit into an LSI.