CURRENT SUBTRACTION CIRCUIT

PURPOSE:To prevent distortion in waveform and fluctuation of a subtraction current caused by the mirror effect. CONSTITUTION:A current is applied to a bias circuit whose input terminal VCS receives a constant voltage and a base voltage is applied to a base of a 1st transistor(TR) 10 via TRs 30,32, a...

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Bibliographische Detailangaben
Hauptverfasser: WATABE YOSHIO, KANAI YASUNORI, SHIMADA NORIJI, NAKAO TAKAHIKO
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:PURPOSE:To prevent distortion in waveform and fluctuation of a subtraction current caused by the mirror effect. CONSTITUTION:A current is applied to a bias circuit whose input terminal VCS receives a constant voltage and a base voltage is applied to a base of a 1st transistor(TR) 10 via TRs 30,32, and the bias circuit applying the base voltage to bases of voltage stabilizing TRs 22,24. The TRs 22,24 for voltage stabilization are connected in opposite polarity and as an emitter follower and both emitters are connected to a base of a 2nd TR 20, then a DC impedance when viewing the TRs 22,24 from the base of the 2nd TR 20 is small because of parallel connection. As a result, even when the fluctuation in the collector voltage of the 2nd TR 20 charges/discharges the base-collector parasitic capacitance, it is possible to make the base voltage of the TR 20 stable. When the base voltage of the TR 20 is made stable, since the collector voltage of the TR 20 is made stable, the base voltage of the TR 10 is made stable, resulting that a subtracted current I0 is made stable thereby making the subtraction current I flowing to a load 18 stable.