SEMICONDUCTOR MEMORY AND LINE BUFFER USED THEREIN

PURPOSE:To constitute an FIFO memory device with simple circuit configuration without a cache memory and to simplify the circuit configuration of a line buffer for this FIFO memory device. CONSTITUTION:In the FIFO memory device, a read line buffer to output data from a memory array is constituted by two stages. That is, by using the master latching circuits 33, 34 of a first stage and the slave latching circuit 37 of a second stage, one side master latching circuit 33 is made a function equivalent to the cache memory to have. Further, the number of the line buffer is reduced by multiplexing the selection of the bit line BL of the memory array with transfer gates 11-14.