JPH0434828B

PURPOSE:To prevent misoperation of LSI by dividing power supply lines for output buffers in different timings in view of supplying the power supply voltages. CONSTITUTION:The individual power supply pads 2a, 2b are respectively provided in accordane with the output buffers 1a1,1a2,..., 1an which operate in synchronization with the clock phi1 and the output buffers 1b1,..., 1bm which operate in synchronization with the clock phi2 in different timing from the clock phi1 or not synchronized with the clock. simultaneously, a power supply voltage VSS is supplied through the different power supply lins 3a, 3b extended from the pad 2a, 2b. Here, if noise n' is applied on the output An of buffer 1an due to the influence of change in output of the output buffers 1a1-1a(n-1), such noise n' is generated at the timing T1 which is different from the timing T2 in which the outputs of 1a1,..., 1an are stabilized. Therefore, there is no fear that an erroneous output signal is latched.