SEMICONDUCTOR STORAGE DEVICE

PURPOSE:To present the malfunctions of a 2-bank memory DBM including two RAMs which are never simultaneously set in the write modes end to improve the operating speed of a computer including the 2-bank memory DBM by preventing the malfunctions of the computer. CONSTITUTION:The write pulse generating...

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Bibliographische Detailangaben
Hauptverfasser: IWABUCHI MASATO, USAMI MASAMI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To present the malfunctions of a 2-bank memory DBM including two RAMs which are never simultaneously set in the write modes end to improve the operating speed of a computer including the 2-bank memory DBM by preventing the malfunctions of the computer. CONSTITUTION:The write pulse generating circuits WPG1 and WPG2 are provided in a 2-bank memory DBM to produce a prescribed internal signal WG1* or WG2* for production of a write pulse WP1 or WP2 based on the clock signals KO1, KO and K1 and supply the WG1* or WG2* to a RAM 1 or RAM2. Thus both signals WG1* and WG2* can be produced independently and for each RAM and with the cycles shifted from each other. Therefore the cycle time is extremely shortened. Then it is possible to produce such a write pulse that can satisfy the prescribed timing conditions even when the cycle time is approximate to the width needed for each write pulse. In such a constitution, the malfunctions of a multi-bank memory can be prevented.