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PURPOSE:To specify data of memory parity error generation by providing a parity correction storage means storing the correction of a parity and a parity correction storage reading means reading the stored data. CONSTITUTION:At the time of reading data, a parity check means 10 performs a parity check...

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1. Verfasser: IWASAKI MANAMI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To specify data of memory parity error generation by providing a parity correction storage means storing the correction of a parity and a parity correction storage reading means reading the stored data. CONSTITUTION:At the time of reading data, a parity check means 10 performs a parity check using reading data and a parity bit. In the case of a parity check, it is transmitted to a parity correction means 11 and written in a storage part 3 after correcting the parity. At this time, the presence of a parity error is transmitted from a parity check means 10 to a parity correction storage means 13 through a parity correction instruction line 12, and a parity correction storage means 13 stores this. Further, it is read out of a processor 1 by a parity correction storage reading means 14. Therefore, when a parity error is generated at the time of DMA transfer, the correction of the parity of the data and the correction of parity can be recognized.