OUTPUT BUFFER CIRCUIT

PURPOSE:To prevent production of malfunction of a device using the output buffer circuit by connecting a resistor between an inverter output terminal of a 1st stage of CMOS inverters of cascade 2-stage connection and a control terminal and controlling a potential of a control signal inputted to a control signal input terminal externally. CONSTITUTION:When a potential close to a power supply voltage VDD is inputted to a control signal input terminal 3 as a control signal C, a leading of a waveform of an input signal (output signal of 1st stage inverter) S of a CMOS inverter of an output stage is almost the same as a signal waveform of an input signal IN, and its trailing is not steep. This is because a current flows to an output terminal of the 1st stage CMOS inverter from the terminal 3 through a resistor R. Thus, the width of an output OUT of the output stage inverter is widened. When a signal with a potential close to ground potential GND is inputted to the terminal 3, the leading of the waveform of the input signal S of the output stage inverter is not steep. Thus, the pulse width of the output signal OUT is made narrow.