METHOD FOR DISPOSING POWER LINE OF SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To reduce a wiring region of a power source around a large cell and to improve an integrated circuit of a semiconductor circuit by obtaining superposing position of a power line and a power wiring from power line disposing information and power wiring possible region information, and generating contact hole position information according to a contact hole determination rule. CONSTITUTION:A DA or CAD processor 1 inputs position data from a power wiring possible region data file 3 determined based on disposing information of a large cell 10 and self-data filter 2 such as signal wiring pattern from it. Power wiring possible region data are divided into power wiring inhibiting regions 11,..., 11 and residual power wiring possible region 12. The processor 1 inputs data from a power wiring position data file 4 to be given, for example, as data disposed with Vcc and Vss in the cell 10, and a contact hole is formed on a region superposed with the region 12. The processor 1 determines the position of the hole according to a determination rule from a contact hole rule file 5 in this region.