METHOD AND CIRCUIT FOR DETECTION OF PARITY ERROR

METHOD AND CIRCUIT FOR DETECTION OF PARITY ERROR

PURPOSE:To detect a parity error when all bits of a memory are inverted. CONSTITUTION:A data bus 6 is separately connected to a memory (A) 4 and a memory (B) 5. A parity generation/check part 2e performs the parity check with use of all bits of the bus 6, and an inversion detecting parity generation...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: ENDO TADANORI, SUZUKI SHINYA
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:PURPOSE:To detect a parity error when all bits of a memory are inverted. CONSTITUTION:A data bus 6 is separately connected to a memory (A) 4 and a memory (B) 5. A parity generation/check part 2e performs the parity check with use of all bits of the bus 6, and an inversion detecting parity generation/ check part 2b performs the parity check with use of a single bit of the bus 6 connected to the memory 4 and a single bit of the bus 6 connected to the memory 5 respectively. A logical operator 7 secures an OR between the outputs of both parts 2a and 2b end outputs the parity result.