SEMICONDUCTOR STORAGE DEVICE

PURPOSE:To exclusively select a writing or a reading operation within a single memory cycle and to write and read within the same memory cycle in parallel by controlling the accessing of a single bus master module. CONSTITUTION:This device is provided with reading/writing circuits of WAMPs 1 to 4, RAMPs 1 to 4, DOBs 1 to 4, DIB 1 to 4, etc., corresponding to each of plural memory cell arrays MCA 1 to 4, the operational modes of the writing/ reading circuits are determined in accordance with control signals LR/W*, UR/W* by which writing/reading operations are divided into the upper and lower sides of the writing/reading circuits and specified. Thus, the writing/ reading operations are carried out within the same cycle and in an optional mode.