MULTI-INPUT NAND CIRCUIT

PURPOSE:To eliminate a change in an operating speed depending on the input state to each terminal Tin by connecting a Pch transistor (TR) TRp and an Nch TRm to each input terminal Tin in an uniform. state. CONSTITUTION:Sources of PchFETs 11-13 are connected to a power supply VCC, three-stages of Nch...

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Hauptverfasser: KATO TAKAHIRO, HACHIGA MORIHIKO
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creator KATO TAKAHIRO
HACHIGA MORIHIKO
description PURPOSE:To eliminate a change in an operating speed depending on the input state to each terminal Tin by connecting a Pch transistor (TR) TRp and an Nch TRm to each input terminal Tin in an uniform. state. CONSTITUTION:Sources of PchFETs 11-13 are connected to a power supply VCC, three-stages of NchFETs 11-13 each are connected between a drain and ground and groups 1a-1c are connected together. Gates of the TRs 11-13 are connected to gates of TRs 14,17,20. One of upper, middle and lower stages of the TR groups 1a-1c is selected and connected to each input terminal Tin1-Tin3 as specified. Thus, the condition to each of the input terminals Tin1-Tin3 in the 3-input NAND circuit is uniform, and even when the input signals Vin1, Vin2 are at an H level and the input signal Vin3 changes from L to H level, and even when the input signals Vin2, Vin3 are at an H level and the input signal Vin1 changes from L to H level, the leading speed of an output signal- Vout is equal and no skew is caused.1.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH04259116A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH04259116A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH04259116A3</originalsourceid><addsrcrecordid>eNrjZJDwDfUJ8dT19AsIDVHwc_RzUXD2DHIO9QzhYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBiZGppaGhmaOxsSoAQD-bh_1</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MULTI-INPUT NAND CIRCUIT</title><source>esp@cenet</source><creator>KATO TAKAHIRO ; HACHIGA MORIHIKO</creator><creatorcontrib>KATO TAKAHIRO ; HACHIGA MORIHIKO</creatorcontrib><description>PURPOSE:To eliminate a change in an operating speed depending on the input state to each terminal Tin by connecting a Pch transistor (TR) TRp and an Nch TRm to each input terminal Tin in an uniform. state. CONSTITUTION:Sources of PchFETs 11-13 are connected to a power supply VCC, three-stages of NchFETs 11-13 each are connected between a drain and ground and groups 1a-1c are connected together. Gates of the TRs 11-13 are connected to gates of TRs 14,17,20. One of upper, middle and lower stages of the TR groups 1a-1c is selected and connected to each input terminal Tin1-Tin3 as specified. Thus, the condition to each of the input terminals Tin1-Tin3 in the 3-input NAND circuit is uniform, and even when the input signals Vin1, Vin2 are at an H level and the input signal Vin3 changes from L to H level, and even when the input signals Vin2, Vin3 are at an H level and the input signal Vin1 changes from L to H level, the leading speed of an output signal- Vout is equal and no skew is caused.1.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920914&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04259116A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920914&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04259116A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KATO TAKAHIRO</creatorcontrib><creatorcontrib>HACHIGA MORIHIKO</creatorcontrib><title>MULTI-INPUT NAND CIRCUIT</title><description>PURPOSE:To eliminate a change in an operating speed depending on the input state to each terminal Tin by connecting a Pch transistor (TR) TRp and an Nch TRm to each input terminal Tin in an uniform. state. CONSTITUTION:Sources of PchFETs 11-13 are connected to a power supply VCC, three-stages of NchFETs 11-13 each are connected between a drain and ground and groups 1a-1c are connected together. Gates of the TRs 11-13 are connected to gates of TRs 14,17,20. One of upper, middle and lower stages of the TR groups 1a-1c is selected and connected to each input terminal Tin1-Tin3 as specified. Thus, the condition to each of the input terminals Tin1-Tin3 in the 3-input NAND circuit is uniform, and even when the input signals Vin1, Vin2 are at an H level and the input signal Vin3 changes from L to H level, and even when the input signals Vin2, Vin3 are at an H level and the input signal Vin1 changes from L to H level, the leading speed of an output signal- Vout is equal and no skew is caused.1.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJDwDfUJ8dT19AsIDVHwc_RzUXD2DHIO9QzhYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBiZGppaGhmaOxsSoAQD-bh_1</recordid><startdate>19920914</startdate><enddate>19920914</enddate><creator>KATO TAKAHIRO</creator><creator>HACHIGA MORIHIKO</creator><scope>EVB</scope></search><sort><creationdate>19920914</creationdate><title>MULTI-INPUT NAND CIRCUIT</title><author>KATO TAKAHIRO ; HACHIGA MORIHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH04259116A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1992</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>KATO TAKAHIRO</creatorcontrib><creatorcontrib>HACHIGA MORIHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KATO TAKAHIRO</au><au>HACHIGA MORIHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MULTI-INPUT NAND CIRCUIT</title><date>1992-09-14</date><risdate>1992</risdate><abstract>PURPOSE:To eliminate a change in an operating speed depending on the input state to each terminal Tin by connecting a Pch transistor (TR) TRp and an Nch TRm to each input terminal Tin in an uniform. state. CONSTITUTION:Sources of PchFETs 11-13 are connected to a power supply VCC, three-stages of NchFETs 11-13 each are connected between a drain and ground and groups 1a-1c are connected together. Gates of the TRs 11-13 are connected to gates of TRs 14,17,20. One of upper, middle and lower stages of the TR groups 1a-1c is selected and connected to each input terminal Tin1-Tin3 as specified. Thus, the condition to each of the input terminals Tin1-Tin3 in the 3-input NAND circuit is uniform, and even when the input signals Vin1, Vin2 are at an H level and the input signal Vin3 changes from L to H level, and even when the input signals Vin2, Vin3 are at an H level and the input signal Vin1 changes from L to H level, the leading speed of an output signal- Vout is equal and no skew is caused.1.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title MULTI-INPUT NAND CIRCUIT
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