LINE CONTROLLER

PURPOSE:To execute stable transfer by holding the data transfer velocity of each line in a common control means and executing arbitration by starting the allocation of the high priority order of a bus request from a serial/parallel data converting means in the order of the high transfer velocity. CONSTITUTION:When no transmitting data are held in serial/parallel data conversion parts 2-1-2-N, those parts turn bus request signal lines 3-1-3-N to logic '1' and execute bus requests. When the plural bus requests are simultaneously executed, based on the contents of a transfer velocity holding part 11, a bus request arbitration part 12 accepts the bus request at the highest data transfer velocity through the signal line 3-1, for example. Then, a bus acknowledge signal line 4-1 is turned to logic '1' and the permission of bus use is applied. The conversion part 2-1 transfers parallel data with a memory under DMA. Thus, under run/over run is hardly generated, stable data transfer is enabled and the data transfer velocity can be set with arbitrary combination.