SYSTEM AND METHOD FOR INSPECTION AND ALIGNMENT AT SEMICONDUCTOR CHIP AND CONDUCTOR LEAD FRAME

SYSTEM AND METHOD FOR INSPECTION AND ALIGNMENT AT SEMICONDUCTOR CHIP AND CONDUCTOR LEAD FRAME

PURPOSE: To improve precision by making the image of a connecting electrode pattern coincide with the image of bonding parts of a lead frame, detecting position attitude difference between two models, adjusting the position attitudes of the thermode, and a gripper, and making the connecting electrod...

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Hauptverfasser: POORU UIRIAMU KOTEASU, KURISUTOFUAA UORUTAA OODEN, TOOMASU MARIO SHIPORA, GUREN UORUDEN JIYONSON, FUIRITSUPU MAAFUII
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator POORU UIRIAMU KOTEASU
KURISUTOFUAA UORUTAA OODEN
TOOMASU MARIO SHIPORA
GUREN UORUDEN JIYONSON
FUIRITSUPU MAAFUII
description PURPOSE: To improve precision by making the image of a connecting electrode pattern coincide with the image of bonding parts of a lead frame, detecting position attitude difference between two models, adjusting the position attitudes of the thermode, and a gripper, and making the connecting electrode pattern coincide with the bonding parts of the lead frame. CONSTITUTION: By comparing the picked up image of a lead frame with the model of bonding parts, abnormal lead frames are detected and classified. A TAB tape can be adjustably moved in the X-dimension, but cannot be moved adjustably in the Y-dimension. A plurality of elements of chip positioning/ bonding system have dimensions which the elements cannot make freely adjustable. While position control functions are shared among various elements of the system, adjustable position control functions overlap can be avoided.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH04233245A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH04233245A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH04233245A3</originalsourceid><addsrcrecordid>eNrjZIgNjgwOcfVVcPRzUfB1DfHwd1Fw8w9S8PQLDnB1DvH09wPLOPp4uvv5uvqFKDiGKAS7-no6-_u5hDqHAFU6e3gGgNUghHxcHYGmBDn6uvIwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUknivAA8DEyNjYyMTU0djYtQAAM8LMn8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SYSTEM AND METHOD FOR INSPECTION AND ALIGNMENT AT SEMICONDUCTOR CHIP AND CONDUCTOR LEAD FRAME</title><source>esp@cenet</source><creator>POORU UIRIAMU KOTEASU ; KURISUTOFUAA UORUTAA OODEN ; TOOMASU MARIO SHIPORA ; GUREN UORUDEN JIYONSON ; FUIRITSUPU MAAFUII</creator><creatorcontrib>POORU UIRIAMU KOTEASU ; KURISUTOFUAA UORUTAA OODEN ; TOOMASU MARIO SHIPORA ; GUREN UORUDEN JIYONSON ; FUIRITSUPU MAAFUII</creatorcontrib><description>PURPOSE: To improve precision by making the image of a connecting electrode pattern coincide with the image of bonding parts of a lead frame, detecting position attitude difference between two models, adjusting the position attitudes of the thermode, and a gripper, and making the connecting electrode pattern coincide with the bonding parts of the lead frame. CONSTITUTION: By comparing the picked up image of a lead frame with the model of bonding parts, abnormal lead frames are detected and classified. A TAB tape can be adjustably moved in the X-dimension, but cannot be moved adjustably in the Y-dimension. A plurality of elements of chip positioning/ bonding system have dimensions which the elements cannot make freely adjustable. While position control functions are shared among various elements of the system, adjustable position control functions overlap can be avoided.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920821&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04233245A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920821&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04233245A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>POORU UIRIAMU KOTEASU</creatorcontrib><creatorcontrib>KURISUTOFUAA UORUTAA OODEN</creatorcontrib><creatorcontrib>TOOMASU MARIO SHIPORA</creatorcontrib><creatorcontrib>GUREN UORUDEN JIYONSON</creatorcontrib><creatorcontrib>FUIRITSUPU MAAFUII</creatorcontrib><title>SYSTEM AND METHOD FOR INSPECTION AND ALIGNMENT AT SEMICONDUCTOR CHIP AND CONDUCTOR LEAD FRAME</title><description>PURPOSE: To improve precision by making the image of a connecting electrode pattern coincide with the image of bonding parts of a lead frame, detecting position attitude difference between two models, adjusting the position attitudes of the thermode, and a gripper, and making the connecting electrode pattern coincide with the bonding parts of the lead frame. CONSTITUTION: By comparing the picked up image of a lead frame with the model of bonding parts, abnormal lead frames are detected and classified. A TAB tape can be adjustably moved in the X-dimension, but cannot be moved adjustably in the Y-dimension. A plurality of elements of chip positioning/ bonding system have dimensions which the elements cannot make freely adjustable. While position control functions are shared among various elements of the system, adjustable position control functions overlap can be avoided.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIgNjgwOcfVVcPRzUfB1DfHwd1Fw8w9S8PQLDnB1DvH09wPLOPp4uvv5uvqFKDiGKAS7-no6-_u5hDqHAFU6e3gGgNUghHxcHYGmBDn6uvIwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUknivAA8DEyNjYyMTU0djYtQAAM8LMn8</recordid><startdate>19920821</startdate><enddate>19920821</enddate><creator>POORU UIRIAMU KOTEASU</creator><creator>KURISUTOFUAA UORUTAA OODEN</creator><creator>TOOMASU MARIO SHIPORA</creator><creator>GUREN UORUDEN JIYONSON</creator><creator>FUIRITSUPU MAAFUII</creator><scope>EVB</scope></search><sort><creationdate>19920821</creationdate><title>SYSTEM AND METHOD FOR INSPECTION AND ALIGNMENT AT SEMICONDUCTOR CHIP AND CONDUCTOR LEAD FRAME</title><author>POORU UIRIAMU KOTEASU ; KURISUTOFUAA UORUTAA OODEN ; TOOMASU MARIO SHIPORA ; GUREN UORUDEN JIYONSON ; FUIRITSUPU MAAFUII</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH04233245A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1992</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>POORU UIRIAMU KOTEASU</creatorcontrib><creatorcontrib>KURISUTOFUAA UORUTAA OODEN</creatorcontrib><creatorcontrib>TOOMASU MARIO SHIPORA</creatorcontrib><creatorcontrib>GUREN UORUDEN JIYONSON</creatorcontrib><creatorcontrib>FUIRITSUPU MAAFUII</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>POORU UIRIAMU KOTEASU</au><au>KURISUTOFUAA UORUTAA OODEN</au><au>TOOMASU MARIO SHIPORA</au><au>GUREN UORUDEN JIYONSON</au><au>FUIRITSUPU MAAFUII</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SYSTEM AND METHOD FOR INSPECTION AND ALIGNMENT AT SEMICONDUCTOR CHIP AND CONDUCTOR LEAD FRAME</title><date>1992-08-21</date><risdate>1992</risdate><abstract>PURPOSE: To improve precision by making the image of a connecting electrode pattern coincide with the image of bonding parts of a lead frame, detecting position attitude difference between two models, adjusting the position attitudes of the thermode, and a gripper, and making the connecting electrode pattern coincide with the bonding parts of the lead frame. CONSTITUTION: By comparing the picked up image of a lead frame with the model of bonding parts, abnormal lead frames are detected and classified. A TAB tape can be adjustably moved in the X-dimension, but cannot be moved adjustably in the Y-dimension. A plurality of elements of chip positioning/ bonding system have dimensions which the elements cannot make freely adjustable. While position control functions are shared among various elements of the system, adjustable position control functions overlap can be avoided.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SYSTEM AND METHOD FOR INSPECTION AND ALIGNMENT AT SEMICONDUCTOR CHIP AND CONDUCTOR LEAD FRAME
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