SYSTEM AND METHOD FOR INSPECTION AND ALIGNMENT AT SEMICONDUCTOR CHIP AND CONDUCTOR LEAD FRAME

PURPOSE: To improve precision by making the image of a connecting electrode pattern coincide with the image of bonding parts of a lead frame, detecting position attitude difference between two models, adjusting the position attitudes of the thermode, and a gripper, and making the connecting electrod...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: POORU UIRIAMU KOTEASU, KURISUTOFUAA UORUTAA OODEN, TOOMASU MARIO SHIPORA, GUREN UORUDEN JIYONSON, FUIRITSUPU MAAFUII
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE: To improve precision by making the image of a connecting electrode pattern coincide with the image of bonding parts of a lead frame, detecting position attitude difference between two models, adjusting the position attitudes of the thermode, and a gripper, and making the connecting electrode pattern coincide with the bonding parts of the lead frame. CONSTITUTION: By comparing the picked up image of a lead frame with the model of bonding parts, abnormal lead frames are detected and classified. A TAB tape can be adjustably moved in the X-dimension, but cannot be moved adjustably in the Y-dimension. A plurality of elements of chip positioning/ bonding system have dimensions which the elements cannot make freely adjustable. While position control functions are shared among various elements of the system, adjustable position control functions overlap can be avoided.