OUTPUT CIRCUIT FOR BICMOS

OUTPUT CIRCUIT FOR BICMOS

PURPOSE: To change an output logic level with full swing of 0V and 5V. CONSTITUTION: NMOSs M7 and M8 are connected to PMOSs M1 and M2 of an inverter, which is connected to an input node N1 and determines the logic state. A PMOS M5 and an NMOS M6 are connected in parallel to output bipolar TRs Q1 and...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: YANAGAWA SAKAE, GEN SHINICHI, KIN EIMIN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PULSE TECHNIQUE
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:PURPOSE: To change an output logic level with full swing of 0V and 5V. CONSTITUTION: NMOSs M7 and M8 are connected to PMOSs M1 and M2 of an inverter, which is connected to an input node N1 and determines the logic state. A PMOS M5 and an NMOS M6 are connected in parallel to output bipolar TRs Q1 and Q2 respectively, and gates of the PMOS M5 and the NMOS M6 are directly connected to a PMOS M3 and an NMOS M4 of an inverter or the input node N1 to drive them. A charging/discharging current of a capacitor C0 flows to the output bipolar TRs Q1 and Q2 , the PMOS M5, and the NMOS M6 in parallel, and the change time is quickened, and transmission is performed without voltage drop and voltage rise around an output node N4, and thus, a full swing is obtained at the time of logic conversion.